Skip to content
View GabbedT's full-sized avatar
🎯
Focusing
🎯
Focusing
5 followers · 2 following

Achievements

Achievement: Starstruck

Achievements

Achievement: Starstruck

Block or report GabbedT

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
GabbedT/README.md

Hi there 👋

I'm a 22-year-old that loves solving problems and dedicated to hard work. My main interests revolve around hardware, especially chip design (FPGAs, ASICs, and more) and low level programming. I hold a Bachelor's degree in Computer Engineering and I'm currently pursuing a Master's degree in Electronic Engineering at Politecnico di Torino, to further deepen my knowledge of computer hardware.

📧 How to reach me:

📚 Currently self studying:

  • RISC-V ISA
  • Embedded Systems
  • Microcontroller programming
  • Verification
  • C++ language

Pinned Loading

  1. ZenithSoC ZenithSoC Public

    General purpose FPGA based System On Chip built around a powerful RISC-V 32 bit CPU.

    SystemVerilog 1

  2. ApogeoRV ApogeoRV Public

    A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

    SystemVerilog 21 2

  3. UART-Controller UART-Controller Public

    UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the d…

    SystemVerilog 6