Immediate operand support for CSR instructions？

[XuanTongYao]

When I use riscv::register::mstatus::set_mie(); to enable global interrupts, the resulting assembly code is quite puzzling.

It does not use the csrsi instruction, but instead uses the csrs instruction.
The csrs instruction uses an additional register.

This causes two problems:

1. Code bloat
2. Toggling global interrupts becomes a non-atomic operation (which contradicts the RISC-V Privileges document)

[XuanTongYao]

The same issue occurs with registers such as mie.

I'm not sure if this is the expected behavior.

[romancardenas]

We use the following macro for setting bit fields in registers:

riscv/riscv/src/register/macros.rs

Line 352 in 187453b

core::arch::asm!(concat!("csrrs x0, ", stringify!($csr_number), ", {0}"), in(reg) bits);

We could explore using csrsi in some cases like the ones you point out to optimize the binary

[XuanTongYao]

For more details on CSR instructions, see here.
In short, in the "Zicsr" extension, we have three CSR instructions and their immediate operand forms:

• CSRRW[I]
• CSRRS[I]
• CSRRC[I]

The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field.

Therefore, the value range of the immediate (uimm[4:0]) is [0,31]. If bits can be calculated at compile time and its value falls within the range of the immediate, we can use the CSR instructions with immediate operands.

[romancardenas]

This is interesting. I have no time now to address this, but it would look like:

unsafe fn _try_set(bits: usize) -> $crate::result::Result<()> {
    match () {
        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
        () => {
             #[cfg(not(target_feature = "zicsr"))]
             core::arch::asm!(concat!("csrrs x0, ", stringify!($csr_number), ", {0}"), in(reg) bits);
             #[cfg(not(target_feature = "zicsr"))]
             core::arch::asm!(concat!("csrrsi x0, ", stringify!($csr_number), ", {0}"), in(reg) bits);
             Ok(())
          }
          #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
          () => Err($crate::result::Error::Unimplemented),
      }
}

Of course, we would need also to check that the immediate is less than 32

[romancardenas]

In any case, looks like target_feature = "zicsr" is not stably supported, so this should wait.

[XuanTongYao]

In the past, CSR instructions were part of the base integer instruction set(RV32I/RV64I), but they have now been removed and are part of the "zicsr" extension.

The Rust toolchain and this repository may not have updated this content; by default, the CSR instruction is available in both.However, not all RISC-V processor cores implement the CSR instruction.