In the multicore.rs example, the other HARTs wait for an interrupt before entering main. However it seems as though there could be a race condition if HART 0 sets the interrupt flag to 1 in
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(addr as *mut u32).write_volatile(1); |
, and then HART 1 sets it to 0 in
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(addr as *mut u32).write_volatile(0); |
.
This would make the interrupt flag be 0, when HART 1 is entering the loop in
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loop { |
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wfi(); |
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if mip::read().msoft() { |
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break; |
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} |
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} |
, and remain 0, because HART 0 has already set the flag, but it was overwritten by HART 1.
In the
multicore.rsexample, the other HARTs wait for an interrupt before enteringmain. However it seems as though there could be a race condition if HART 0 sets the interrupt flag to 1 inriscv/riscv-rt/examples/multi_core.rs
Line 47 in 95cfb90
riscv/riscv-rt/examples/multi_core.rs
Line 19 in 95cfb90
This would make the interrupt flag be 0, when HART 1 is entering the loop in
riscv/riscv-rt/examples/multi_core.rs
Lines 24 to 29 in 95cfb90